What will computer chips look like in 2045?

Dwarkesh Podcast · 2026-10-22

What will computer chips look like in 2045?Dwarkesh Podcast ▶ Play the video

Why it earned a slot

The Intel fab tour in “What will computer chips look like in 2045?” delivers a tactile sense of where transistor technology is heading—gate-all-around, backside power, CFET, hybrid bonding—all framed against a 20-year horizon. It’s a rare glimpse into the manufacturing pipeline that underpins the compute constraints discussed in episodes 1 and 3, making it a must-listen for anyone budgeting future AI infrastructure.

The short version

Future chips: from silicon to system-level alchemy.

Why it matters

AI workloads will soon outgrow the performance headroom of today’s nodes, and the next generation of packaging and interconnects will dictate the cost curve of training and inference. Understanding these roadmaps now lets you align your roadmap with the hardware that will actually be available when your models hit production scale.

My take

I’d argue that the most impactful shift will be in 3-D integration—CFET and hybrid bonding will collapse the memory-compute gap, enabling tighter model parallelism. Teams that design for these constraints early will avoid costly redesigns later.

How it connects

• Packaging economics → echoes the rectangular compute discussion in episode 1.
• 3-D integration → will enable the superagent workloads highlighted in episode 4.
• Hardware-software co-design → reinforces the engineering principles from episode 3.

Bottom line

Start incorporating 3-D integration constraints into your hardware planning documents.